Course Developers and Instructors

Verilog

Mike Ciletti Ph.D., Professor of Electrical and Computer Engineering, University of Colorado

Dr. Ciletti is a professor of electrical and computer engineering at the University of Colorado at Colorado Springs.  He has developed and presented several short courses to engineers in the United States, Asia  and Europe treating the design and synthesis of application specific integrated circuits (ASICs) using Verilog, and is active as a consultant for Verilog-based modeling and synthesis.  He also developed and presented several short-courses at the annual meetings of Open Verilog International (now Accellera) and was a balloting member for IEEE Std. 1364-1995.

Dr. Ciletti is the author of the following well-respected verilog textbooks:

  • Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL
  • Advanced Digital Design with the Verilog HDL
  • Starter’s Guide to Verilog 2001

Steven E. Start , Independent Consultant

Mr. Start has over 15 years of engineering experience in electrical engineering and software development.  He possesses a broad range of practical engineering experience including real-time embedded systems development, EDA Tool technical support, EDA library development, front and back-end digital ASIC design methodology development, and industrial instrumentation and control.  His career includes working for Argonne National Laboratory and AMI Semiconductor, and work as a consultant.  While at AMI Semiconductor, he prepared and taught several classes on EDA point-tools and design flow.  Mr. Start has authored and co-authored several original technical papers, two of which received Synopsys User’s Group 1st place best paper awards (Boston 2000, 2001).  Mr. Start was a balloting member of the IEEE Design Automation Standard Committee and participated in the IEEE 1364 Verilog Hardware Description Language standard revision (2001).  He served as a technical committee member for the International Symposium on Quality Electronic Design (ISQED) including serving as chairman and co-chairman for the EDA Tools/Design Methodology Subcommittee in 2000 and 2001.  He holds a Bachelor of Science in Electrical Engineering and a Master of Science degree in Computer Engineering.  Steve currently contracts engineering design work related semiconductor work as an independent contractor.

Charles Dancak, Independent Consultant

Mr. Dancak is an independent consultant and course developer specializing in HDL-based ASIC/FPGA synthesis and DFT.  Mr. Dancak spent ten years at Synopsys, where he developed several of that company’s most highly-rated and successful customer-training workshops. Prior to joining Synopsys, he was employed at Cadence, Teradyne, Silicon Compilers, and Intel. He has traveled across North America, Europe, and Asia, presenting EDA workshops and seminars to hundreds of design engineers interested in getting the most out of the languages and their tools.

Mr. Dancak has worked with Verilog and VHDL since 1992, is fluent in both, and currently teaches basic and advanced extension classes in HDL-based design and verification at the University of California, Santa Cruz.  He has an MSEE from the University of Wisconsin, and an MS in Solid-State Physics from the Polytechnic University of New York.

Chuck Mangan, Independent Consultant

Mr. Mangan is an electrical engineer with 20 years experience in design, manufacturing, test, and project management. He is considered an authority in IC Verification using Verilog, Specman, and Vera and in IC Design using Verilog.  Mr. Mangan has worked on and managed IC and FPGA design and verification projects from 10,000 to 20M gates. He has presented at conferences and is the author of the well known “e Language Field Guide”.

Mr. Mangan has also used his expertise to instruct many engineers in the art and methodology of verification and reuse via beginning and expert classes in designing with Verilog and in verification using Verilog, Specman, and Vera. He continues to work as a consultant now through his own company, and teaches classes in design and verification for TM Associates.

VHDL

 Peter Ashenden

Dr. Peter Ashenden is a recognized expert in the VHDL language.  He has been actively involved in IEEE working groups developing VHDL standards.  At the present time he serves in the following capacities:

  • Standards Editor and Member of Editorial Board for “IEEE Design & Test of Computers”
  • Vice Chair of IEEE Design Automation Standards Committee
  • Co-editor of Series in Systems on Silicon for Morgan Kaufmann Publishers
  • Member of System-Level Design Language Committee of Accellera and European CAD Standards Initiative
  • Member of IEEE Design Automation Standards Committee and four working groups

In addition, Dr. Ashenden is also involved in the development of the Rosetta system-level design language, and is Technical Editor for the Draft Standard Rosetta Language Reference Manual being prepared by the Accellera SLDS Rosetta Committee.

Dr. Ashenden is a prolific author on VHDL.  His work includes the following:

Books ( Morgan Kaufman, Publisher):

  • System Designer’s Guide to VHDL-AMS
  • Designer’s Guide to VHDL, second edition
  • Student’s Guide to VHDL

Reports – 22

Publications – 33

Workshops – 5

Research Grants – 7

Dr. Ashenden received his B.Sc.(Hons) and Ph.D. from Adelaide University, South Australia. He is an independent consultant specializing in electronic design automation (EDA).  His research interests are electronic design automation and computer architecture. He is a Senior Member of the IEEE and a member of the ACM.

Patrick McCabe

Patrick (Pat) McCabe has over 20 years of ASIC, FPGA and system design experience. Mr. McCabe has extensive experience with top-down design techniques, verification, system simulation, behavioral model development, hardware/software co-simulation and co-verification, coverage measurement tools, and performance measurement techniques. In addition, he is highly experienced with Synopsys tools and the ModelSim simulator, and has been using VHDL and Synopsys since 1989. In addition to gate-array and full-custom design experience using IBM, NEC, and proprietary technologies, his FPGA experience includes the use of Xilinx, Altera, and Actel FPGA’s. In addition, he has used 3rd party IP cores from various companies, including embedded ARM microprocessor cores.

Mr. McCabe has worked for various companies, including Intel, IBM, Cirrus Logic, Honeywell, and was also a founder of Basis Communications. His experience ranges from communications systems, to state-of-the-art microprocessor design, to space-borne computers, to industrial controls. Mr. McCabe has been responsible for the creation of a VHDL-based design methodology at a number of companies. On various projects, Mr. McCabe has held positions of lead hardware engineer, lead verification engineer and lead systems engineer. Mr. McCabe has also taught internal classes at various companies on VHDL-based design techniques.

Mr. McCabe has presented papers on bus functional model design and system simulation at the VHDL International User’s Forum (VIUF), and has also been a session chair for that conference.

Mr. McCabe holds both Bachelor of Science and Master of Science degrees in Computer Engineering. He holds a U.S. patent for the design of a frame relay ASIC, and is also a member of the IEEE.

Ken Banas

Ken Banas has been involved in ASIC and FPGA work for over 14 years.  He has been involved in all aspects of the design process including process setup and documentation, design definition and documentation, RTL design and verification, synthesis, and static timing.  His most recent emphasis is on timing closure for high-speed multi-million gate chips.  His design experience has been with both VHDL and Verilog and he has taught numerous internal design process classes throughout his career.  Mr. Banas has extensive experience with RTL, behavioral, and structural HDL design techniques using both synchronous and asynchronous methods.  His specialty has been to understand the complete design process.  He has lead all steps of the process from product conception to chip and system validation in the lab.

Mr. Banas is currently focusing on state of the art timing closure techniques for complex chips involving dozens of clock domains, numerous hard and soft IP macros, with data rates in the multiple-gigahertz range. He has thorough knowledge of high speed synthesis techniques including physical synthesis.

Mr. Banas has worked for IBM, GE, Honeywell, Paradyne Corp., Cirrus Logic, Basis Communications and Intel. His responsibilities have ranged from ASIC designer to Lead Electrical Engineer for a military missile computer which included multiple boards and ASICs.

Mr. Banas has an M.S.E.E. from the University of South Florida and a B.S.E.E from Syracuse University. He holds a U.S. patent for the design of a DSL modem packet-processing ASIC, and is also a member of the IEEE.