2 Days, Basic Level
The Verilog hardware description language plays a key role in design flows for ASICs and FPGAs. It is increasingly important that people involved with hardware design have a background in this language and an awareness of the features introduced by IEEE Std 1364-2001.
This course provides a basic introduction to the main features of the Verilog language. The course will familiarize the student with the language and bridge the gap between the basic concepts in digital logic (schematics, Boolean equations, truth tables, etc.) and related constructs used in Verilog-based design flows. Several examples will illustrate language features, including an introduction to modeling styles suitable for simulation and synthesis.
Upon completion of this course, students will:
- understand basic language concepts and usage
- understand the role of Verilog in ASIC and FPGA design flows
- understand the use of Verilog in top-down design methodology
- be able to write simple models of combinational and sequential logic
- write and execute a test plan and develop a testbench for verifying a model
- be able to run a simulator to verify a model
- understand the enhancements introduced by Verilog 2001
Verilog Introduction is recommended for technical personnel with little or no knowledge of Verilog who need to learn the language for understanding someone else’s code. Managers and engineering support people will benefit from this course.
For people who need to learn Verilog for designing, it is recommended that they take the 4-day Verilog for Hardware Designers which covers more of the language and has extensive labs.
Students need to be familiar with the basics of digital design of combinational and sequential logic.
Suggested follow-on course:
Advanced Verilog Coding Styles for Synthesis & Verification
This is an intensive, interactive course, which is approximately 70% lecture and 30% lab. Questions are highly encouraged.
Day 1: Introduction to Modeling and Verification with Verilog
Getting Started with Verilog
Structural Models of Combinational and Sequential Logic
Hierarchical Decomposition and Top-down design
Testbenches, Simulation, and Model Verification
Day 2: Behavioral Modeling with Verilog
Behavioral Models of Combinational Logic
Behavioral Models of Sequential Logic
Additional Topics for Testbenches
Tasks and Functions