“My time was well spent. Lots of information, no time to slack off.”
Staying competitive in today’s ASIC/FPGA market means designing ICs with greater functionality, higher speed, and lower cost. Effective VHDL coding techniques can make all the difference between designs that meet tough synthesis targets and verification schedules, versus those requiring re-spins. The goal of this hands-on workshop is to enhance your mastery of VHDL language features which drive the synthesis tool and maximize verification productivity. Most of the material is tool-neutral, although case studies include results for popular ASIC/FPGA tools. Each key principle or coding insight is shown in the context of a realistic design situation. You’ll be exposed to a wireless-telephony chip design, both in lectures and labs. Digital video and graphics applications are also explored. This course can be customized or condensed to meet the specific needs of your design team or available schedule.
Upon completion of this course, you will:
- Understand and apply VHDL coding techniques which synthesize efficiently, while avoiding common pitfalls.
- Be able to visualize the synthesized logic which results from specific VHDL constructs and coding styles.
- Gain experience in coding with a specific architecture in mind, which implements the required logic function while meeting speed or area targets — through parallelization, resource sharing, and other HDL coding techniques.
- Be able to tap into the full diversity of simulatable VHDL constructs for verification, following practical IC verification strategies and writing more effective testbenches.
This course is recommended for IC designers already familiar with basic VHDL syntax, but who want to use the features of VHDL more effectively to synthesize blocks that meet specific timing and area targets. The third day of the workshop focuses on VHDL coding for testbenches, and is positioned for designers who need to understand verification issues, as well as verification engineers who want a firmer grasp of language subtleties.
Students need to have a working knowledge of basic VHDL.
This is an intensive, interactive course, which is approximately 50% lecture and 50% lab. Questions are highly encouraged.
Unit 1: Introduction Coding and synthesizing a typical VHDL module to be used in the wireless chip.
Unit 2: Combinational Logic
Unit 3: Sequential Logic
Unit 4: Block Integration
Unit 5: FSMs and Controllers
Unit 6: Getting the most out of your tools
Unit 7: Coding for Area
Unit 8: Coding for Performance
Unit 9: Verification
Unit 10: Testbench Techniques
Unit 11: Avoiding Simulation Pitfalls
Unit 12: Advanced Topics
Lab 1–12You will apply coding techniques covered in lecture to synthesize and verify, block by block, a wireless telephony chip that meets functional specs and achieves target clock frequency.